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I don't like the variable names, I think it's confusing especially in the 
Python part which is the user part. "lookup_latency"  does not clearly refer to 
the tag lookup action , and "ram_latency" is also not very clear. Maybe 
something like "tag_latency" and "line_latency" could be better ? I think the 
two parts of a cache are well identified in this example.

- Pierre-Yves Péneau


On June 16, 2016, 8:55 p.m., Sophiane SENNI wrote:
> 
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> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3502/
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> 
> (Updated June 16, 2016, 8:55 p.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> -------
> 
> Changeset 11536:1a3a96d435ed
> ---------------------------
> cache: Split the hit latency into tag lookup latency and RAM access latency
> 
> If the cache access mode is parallel ("sequential_access" parameter set to 
> "False"), tags and RAMs are accessed in parallel. Therefore, the hit latency 
> is the maximum latency between tag lookup latency and RAM access latency. On 
> the other hand, if the cache access mode is sequential ("sequential_access" 
> parameter set to "True"), tags and RAM are accessed sequentially. Therefore, 
> the hit latency is the sum of tag lookup latency plus RAM access latency.
> 
> 
> Diffs
> -----
> 
>   src/mem/cache/tags/fa_lru.hh 80e79ae636ca 
>   src/mem/cache/tags/base.cc 80e79ae636ca 
>   src/mem/cache/tags/Tags.py 80e79ae636ca 
>   src/mem/cache/tags/fa_lru.cc 80e79ae636ca 
>   src/mem/cache/tags/base_set_assoc.hh 80e79ae636ca 
>   src/mem/cache/tags/base.hh 80e79ae636ca 
>   configs/common/Caches.py 80e79ae636ca 
>   src/mem/cache/Cache.py 80e79ae636ca 
>   src/mem/cache/base.hh 80e79ae636ca 
>   src/mem/cache/base.cc 80e79ae636ca 
> 
> Diff: http://reviews.gem5.org/r/3502/diff/
> 
> 
> Testing
> -------
> 
> Tested using --Debug-flags=Cache
> 
> 
> Thanks,
> 
> Sophiane SENNI
> 
>

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