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This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3502/
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(Updated juin 16, 2016, 3:27 après-midi)
Review request for Default.
Repository: gem5
Description
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Changeset 10875:dd94e2606640
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cache: Split the hit latency into tag lookup latency and RAM access latency
If the cache access mode is parallel ("sequential_access" parameter set to
"False"), tags and RAMs are accessed in parallel. Therefore, the hit latency is
the maximum latency between tag lookup latency and RAM access latency. On the
other hand, if the cache access mode is sequential ("sequential_access"
parameter set to "True"), tags and RAM are accessed sequentially. Therefore,
the hit latency is the sum of tag lookup latency plus RAM access latency.
Diffs (updated)
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src/mem/cache/tags/fa_lru.cc UNKNOWN
src/mem/cache/tags/fa_lru.hh UNKNOWN
src/mem/cache/tags/base_set_assoc.hh UNKNOWN
src/mem/cache/tags/base.cc UNKNOWN
src/mem/cache/tags/base.hh UNKNOWN
src/mem/cache/tags/Tags.py UNKNOWN
src/mem/cache/base.hh UNKNOWN
src/mem/cache/base.cc UNKNOWN
src/mem/cache/BaseCache.py UNKNOWN
configs/common/Caches.py UNKNOWN
Diff: http://reviews.gem5.org/r/3502/diff/
Testing
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Tested using --Debug-flags=Cache
Thanks,
Sophiane SENNI
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