> I'll give the short version here: MIPS was implemented ot use the MT ISA > extension > which requires the ability to read/write registers from other threads. I > designed the register file > to be on size fits all. It can be instantiated multiple times as a > per-thread register file (Simple-CPU) OR > it could be used as one big physical register file to allow threads > communicate with each other (InOrder model). > This differs since O3 defines it's own physical register file instead of the > pre-defined one in the src/arch folder. > > There is one patch that I need to send out that merges the two solutions > together where I add a thread-ID to > all the thread-context functions cpu/thread_context.* and then defaulted > that value to 0. This in effect allowed > the other ISAs (ALPHA/SPARC/etc.) to compile and run unaffected by the > changes I made. I'm not sure the other > ISAs will ever "care" about communicating between register files so I though > that was an OK solution.
Instead of this, couldn't you do the cross thread thing by looking up the appropriate thread context in the cpu object and then calling the register access function for that thread context? This would work more in line with the other CPU models. Nate _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
