Dear M5 Team, I'll soon start to work on integrating our M5-based simulator, MV5, into M5. I've read some documentation on the current status of M5, and I'd like to share my plan/ideas with you and hear your suggestions. Since M5 will soon replace its entire memory system modeling with Ruby&Gems, it seems the interconnect and directory coherence modules in MV5 will have little value for future M5. I'm wondering if the following contributions would be interesting to you.
1. An in-order CPU module with multi-threading (switching threads upon cache accesses) based on TimingSimpleCPU. 2. SIMD cores: Based on TimingSimpleCPU. It models GPU-like branch handling using the re-convergence stack. It is implemented as an array of scalar threads rather than wider vector registers. It requires a parallel API written in a similar style to OpenMP, with manually instrumentation to signal the end of a branch in the parallel section of code. 3. A parallel API for writing parallel benchmarks that run in system emulation mode. It can be used in a similar way to Pthread. It also provide OpenMP-like programming interface, and it can work with the SIMD cores. It also comes with various scheduling policies. 4. A batch-simulation tool, which creates, manages, organizes, and analyzes simulation tasks in batches. Written in Python. Good for space exploration and sensitivity study. I manage tens of thousands of simulations over up to 100 machines using this tool. It can work with a cluster of machines with a shared file system. It also supports the PBS queuing system. What do you think about the above contributions? Can you prioritize them? Thanks, Jiayuan
_______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
