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src/arch/arm/tlb.cc <http://reviews.m5sim.org/r/342/#comment812> It seems to me like we ought to have a generic check in the CPU models that prevents prefetches to uncacheable locations rather than burying this in the TLB and requiring every ISA to make this check. (Which leads to the question of how/whether this is handled in other ISAs...) - Steve On 2010-12-06 16:12:26, Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/342/ > ----------------------------------------------------------- > > (Updated 2010-12-06 16:12:26) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > O3: Fixes the way prefetches are handled inside the iew unit. This patch > prevents the prefetch being added to the instCommit queue twice. > > > Diffs > ----- > > src/arch/arm/faults.hh 2b5fbdcbfb5d > src/arch/arm/tlb.cc 2b5fbdcbfb5d > src/cpu/o3/iew_impl.hh 2b5fbdcbfb5d > > Diff: http://reviews.m5sim.org/r/342/diff > > > Testing > ------- > > > Thanks, > > Ali > >
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