> On 2010-12-21 17:29:39, Steve Reinhardt wrote: > > src/arch/arm/tlb.cc, line 562 > > <http://reviews.m5sim.org/r/342/diff/1/?file=5459#file5459line562> > > > > It seems to me like we ought to have a generic check in the CPU models > > that prevents prefetches to uncacheable locations rather than burying this > > in the TLB and requiring every ISA to make this check. (Which leads to the > > question of how/whether this is handled in other ISAs...)
Prefetches aren't implemented in Alpha so this hasn't been an issue. I don't know that I agree it should be in a generic place because I don't know that uncachable is equivalent to non-prefetchable. For example, an memory could be marked cacheable but not prefetchable in sparc if memory serves (same is probably true for some ASI accesses). I think the TLB really needs to make the decision because it's got all of the relevant information. - Ali ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/342/#review559 ----------------------------------------------------------- On 2010-12-06 16:12:26, Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/342/ > ----------------------------------------------------------- > > (Updated 2010-12-06 16:12:26) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > O3: Fixes the way prefetches are handled inside the iew unit. This patch > prevents the prefetch being added to the instCommit queue twice. > > > Diffs > ----- > > src/arch/arm/faults.hh 2b5fbdcbfb5d > src/arch/arm/tlb.cc 2b5fbdcbfb5d > src/cpu/o3/iew_impl.hh 2b5fbdcbfb5d > > Diff: http://reviews.m5sim.org/r/342/diff > > > Testing > ------- > > > Thanks, > > Ali > >
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