Ian Chapman wrote:
> I do not see how ghdl
> can simulate putting 29 bits into an 8 bit vector.
like this ^^ :
library ieee;
use ieee.std_logic_1164.all;
package blabla is
function "+"(a,b:std_logic_vector)return std_logic_vector;
end package;
package body blabla is
function "+"(a,b:std_logic_vector)return std_logic_vector is
begin
return a(a'range);
end;
end package body;
library ieee;
use ieee.std_logic_1164.all;
use work.blabla.all;
entity test is
end entity;
architecture rtl of test is
signal reg_a:std_logic_vector(15 downto 0);
signal carry:std_logic;
begin
reg_a(7 downto 0) <= reg_a(7 downto 0) + (x"0000000" & carry);
end architecture;
Lattice probably assume that "+" operator return the same size as inputs
but I haven't found any constraint in vhdl standard.
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