On Mon, 2009-01-12 at 10:02 +0100, Sylvere Teissier wrote:
> Le dimanche 11 janvier 2009 à 21:31 -0500, Ian Chapman a écrit :
> > Thanks for the clarification Sylvere,
> > I guess it's not a bug after all just a loose end in 1164. I guess
> > that all the words about strict type checking is not that well
> > implemented in the standards. Thanks again for the clarification Ian.
> >
>
> Futhermore, if Lattice is a synthesis tool it can check the output
> vector length of the "+" operation because a synthesis tool use
> techniques like function expansion, loop unrolling and constant
> propagation that permit to have more information and more checking.
> Theses techniques are only applicable on a subset a VHDL (for example
> synthetizable code).
> A simulator is more generalist and check result at run-time after "+"
> function call. (well known "bound check failed")
Thanks again for the information.
One thing that I have noticed as I get my design debugged is that there
are a few things I can specify in hdl or ghdl that may be okay except
that they will not fit into my or any FPGA. Like you need a mux or
three state signal to do one of the things I was trying to do. That or
maybe I needed to debug a bit more to get that far with ghdl.
I guess that is part of learning. Regards Ian.
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