Hi all, Yes, a while ago I also wrote a VHDL-2008 to -93 converter in Tcl, but again, similar to Adrien, mine is also a _really_ simple converter to do only the things I needed.
Perhaps we can work on somethi ng like this again, or like Tristan said, we could also create gate-level (structural) netlist directly which we can input to any major synthesis tool. I'm currently exploring both options. Which do you think is easier? I currently am able to hand-code some things from VHDL-2008 to -93 syntax, even for things like type generics and package generics. What I did was to manually fix the types (or subtypes) in the hand-coded '93 output. To write a program to do that would be quite trivial (in my opinion). Same goes to other '08 features such as enhanced bit string literals, and simplified conditionals. Simplified process sensitivity lists is a bit more tricky though (I need to write something that detects all non-clocked inputs in a process, then add it into an array of signals for the sensitivity list. Another option is to write out a gate-level netlist, based on common standard cells. Different vendors may have different naming conventions for their cells, but these can be easily mapped later on. I know Altera uses something called the LMF (library mapping file) which maps a cell (e.g. called "MUX2_1") from another tool vendor to Altera's own "MUX2" (not actual names; just an example). I believe same goes with the other FPGA and ASIC vendors (we can create mapping files to map between all these major vendors). The tricky part in the case of building our own gate-level netlister would be to figure out the semantics of the VHDL design, and write out the structural netlist. We need to be able to parse the input VHDL, figure out an equivalent circuit for that, and then try and map that into standard cell libraries. I don't know if there are existing open-source VHDL parsers that is able to do this. For simple things like say, " a <= b xor c ", we should be able to write a mapper directly, but to generate a circuit out of a complex state-machine (for example), I really have no idea on how to do that. Does anyone have an idea? regards, daniel On 27 April 2014 15:11, <[email protected]> wrote: > > VHDL-2008 standard support would indeed be great at least for > > simulation. For actual synthesis, the issue is the support by > > commercial > > FPGA vendor tools (amond others). They advertise support of VHDL-93, > > sometimes 2002 (and sometimes also a reduced set of constructs from > > VHDL > > 2008). But the general trend is stick to VHDL-93. > > > > So I was thinking of a more source-to-source approach: convert > > VHDL-2008 > > syntax into VHDL-93 (when possible of course). > > For that, I was thinking of the Clang approach: Clang is a great > > library > > for parsing, reformating, ans as front-end/parser for compilation. > > > > I think it would be great to have something similar for VHDL : build > > a > > VHDL parser as a general-purpose library, which could be used as > > front-end for simulation, conversion to a reasonably structural > > representation for input to any synthesis tool, do 2008->93 > > reformating > > if it's the only possible way etc. > > This approach would also de-duplicate some of the work of building > > synthesis tools by FPGA vendors. This could be relevant for non-major > > FPGA vendors (say others than Xilinx or Altera). > > > > But I have never written fully compliant VHDL parsers. Some time ago > > I > > needed to parse of a _very_ reduced set of the syntax so I made a > > personal chunk of code to achieve only what I needed but that's all. > > Could some GHDL code be reused for that purpose ? > > Is it too big to be done ? > > > > Any thoughts about this ? > > There is already some support for that: for example, you can display > as vhdl your code after canonization (where concurrent statements > are translated to process statements). > > So, yes GHDL could be used for that purpose (it may require a few > adjustments). Note that all 2008 features may not be easily > translated to vhdl 93. > > It could be simpler to create a synthesis tool from GHDL and > translate your design to a low-level RTL code. > > Tristan. > > _______________________________________________ > Ghdl-discuss mailing list > [email protected] > https://mail.gna.org/listinfo/ghdl-discuss >
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