> Hi all, > Yes, a while ago I also wrote a VHDL-2008 to -93 converter in Tcl, > but again, similar to Adrien, mine is also a _really_ simple > converter to do only the things I needed. > > Perhaps we can work on somethi ng like this again, or like Tristan > said, we could also create gate-level (structural) netlist directly > which we can input to any major synthesis tool. > > I'm currently exploring both options. Which do you think is easier? > > I currently am able to hand-code some things from VHDL-2008 to -93 > syntax, even for things like type generics and package generics. > What I did was to manually fix the types (or subtypes) in the > hand-coded '93 output. To write a program to do that would be quite > trivial (in my opinion). Same goes to other '08 features such as > enhanced bit string literals, and simplified conditionals. > Simplified process sensitivity lists is a bit more tricky though (I > need to write something that detects all non-clocked inputs in a > process, then add it into an array of signals for the sensitivity > list. > > Another option is to write out a gate-level netlist, based on common > standard cells. Different vendors may have different naming > conventions for their cells, but these can be easily mapped later > on. I know Altera uses something called the LMF (library mapping > file) which maps a cell (e.g. called "MUX2_1") from another tool > vendor to Altera's own "MUX2" (not actual names; just an example). I > believe same goes with the other FPGA and ASIC vendors (we can > create mapping files to map between all these major vendors).
Altera used LPM, but I am not sure if this is still true. Synopsys has a GENTECH library, but it is not public. Looks like there is no standard here... > The tricky part in the case of building our own gate-level netlister > would be to figure out the semantics of the VHDL design, and write > out the structural netlist. We need to be able to parse the input > VHDL, figure out an equivalent circuit for that, and then try and > map that into standard cell libraries. I don't know if there are > existing open-source VHDL parsers that is able to do this. For > simple things like say, " a <= b xor c ", we should be able to write > a mapper directly, but to generate a circuit out of a complex > state-machine (for example), I really have no idea on how to do > that. Does anyone have an idea? My idea is just that: lowering the design into RTL (i.e. flip-flops, latches and combinational logic). Inferring FF and memory isn't trivial, so I may start with simple algorithms. Tristan. _______________________________________________ Ghdl-discuss mailing list [email protected] https://mail.gna.org/listinfo/ghdl-discuss
