On 28 April 2014 23:29, <[email protected]> wrote: > Le 2014-04-27 09:07, [email protected] a écrit : > > I have started an effort for synthesis, but it is currently too >> preliminary. >> > > you... you... are really doing this ? > > I think it's time you file a request for a grant > from all the open source/free software foundations. >
I would be happy to contribute to such a project. I believe Adrien (and others) would too. We need to carefully choose which language to use though. I don't mind using Ada / VHDL for such an effort (perhaps it's not a bad idea to move synthesis / simulation tools into a chip), but again, we can have a more elaborate discussion on this. I believe there's already enough interest! < Perhaps we can work on somethi ng like this again, or like Tristan said, we could also create gate-level (structural) netlist directly which we can input to any major synthesis tool. /> Sorry, I meant "we could also create a gate-level netlist directly which we can input to any major _place-and-route_ tool." regards, daniel
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