Hi, I agree. I could also add that the way the VHDL code is written can > reveal very interesting implementations (usage of functions etc). > Flattening the design representation down to something too structural > can be anti-productive. It can obfuscate many hardware "factorization" > opportunities. The task of flattening a design description into a > netlist representation should be entirely left to the logic synthesis > tools (proprietary or not). >
Yes. Many things in VHDL are so abstract that it's hard to generate a netlist without figuring out about the abstractions. And I feel a pre-synthesis tool is good at doing these sort of tasks. Take configurations for example. Absolutely no netlist (zero circuitry) needs to be generated from that code. The resulting code will be generated from only the architecture that the end user selected in the configurations. We need a program to figure out from the configuration, which architecture the user has selected, then elaborate only that architecture while ignoring any other architectures. Something like this, in my opinion, is best left to the pre-synthesis tool to handle. Similarly, for generic types, the generics themselves do not map to any form of circuitry. It's the final datatypes chosen by the end user (the user "chooses" the final type to use by means of type generics) that gets synthesised to hardware. cheers, dan
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