Hi, > In the end you have to use the vendor specific tools for place & route > and bitstream generation. But because these tools are free for the > most useable chips, thats not a real problem or a high barrier. The > same for synthesis tools, which are mostly free for personal use these > days...
No these tools are free only for a very reduced subset of the vendors' chips, and this subset is composed of the lowest-grade ones. At least for Xilinx, WebPack edition. You also has to log on their website to download this very limited toolchain. > Why do I "have" to sign a licence agreement, > lock my computer(s) with their flexlm and can't > look at the source code to help myself in case of > a problem ? That's the difference between "it works" > and "it will work well for everybody for as long as we care". > > A typical license lasts one year, which is very short > for some of my projects or the support i must provide. > Which is why I care so much about FOSS. I totally adhere to that way of thinking. > If we could generate gate-level structural code out of these basic > rules [clocks, conditionals (if-elsif-else, case, with-select-when), > and logic], I think that's a good start. For more abstract things like > type/package/subprogram generics, or packages, configurations, etc., > perhaps this is where the presynthesis tool (converts between the more > abstract VHDL-2008 to simple VHDL-93) kicks in. I could help in this > area. Some things, for example configurations, just tell the synthesis > tool which architecture to synthesise, so our pre-compiler could > figure that out and generate the simple VHDL-93 code without > configurations, instead using a fixed architecture for example. Same > thing goes for generic types - our pre-compiler can set the types to > fixed values based on what's been selected by the user at the top > level of the design. I agree. I could also add that the way the VHDL code is written can reveal very interesting implementations (usage of functions etc). Flattening the design representation down to something too structural can be anti-productive. It can obfuscate many hardware "factorization" opportunities. The task of flattening a design description into a netlist representation should be entirely left to the logic synthesis tools (proprietary or not). Regards, Adrien _______________________________________________ Ghdl-discuss mailing list [email protected] https://mail.gna.org/listinfo/ghdl-discuss
