> On 28 April 2014 23:29, < [email protected] > wrote: > > > Le 2014-04-27 09:07, [email protected] a écrit : > > > > I have started an effort for synthesis, but it is currently too > preliminary. > > you... you... are really doing this ? > > I think it's time you file a request for a grant > from all the open source/free software foundations. > > > > I would be happy to contribute to such a project. I believe Adrien > (and others) would too. > > We need to carefully choose which language to use though. I don't > mind using Ada / VHDL for such an effort (perhaps it's not a bad > idea to move synthesis / simulation tools into a chip), but again, > we can have a more elaborate discussion on this. I believe there's > already enough interest!
I don't plan to optimise or target a specific architecture. So I plan to target one of the standard netlist format that could be read by other tools (such as ABC). This part of synthesis is quite language dependent so I plan to reuse most of GHDL. Tristan. _______________________________________________ Ghdl-discuss mailing list [email protected] https://mail.gna.org/listinfo/ghdl-discuss
