Hello,
has anyone tried to compile the Altera (VHDL) libraries for GHDL?
I found the complete simulation models in "C:\Altera\15.0\quartus\library\sim_lib\..." as VHDL and Verilog files. I tried to compile them but hit some problems:
1) Altera uses non standard IEEE packages, so I needed to configure GHDL with -ieee=synopsys.
1.1) Why is -ieee=mentor|synopsys not listed as a GHDL option anymore?
1.2) GHDL implecitely creates comparision operator(s) for std_logic_vector in std_logic_1164.v93 (">=") which collides with numeric_std.
I used -fexplicit as workaround, but is it correct behavior of GHDL to generate a ">=" operator?
2) One file has non ASCII chars (c) and TM in it - inserted in a comment line. Nice new error message :).
I think I should write a bug report to Altera, because GHDL won't relax on this rule, will it? ;)
3) There are dozens of bound errors complaining about bounds being no universal integer or attribute. Example
entity foo is
generic (
Width : natural
)
[...]
end entity;
architecture rtl of foo is
type mem is array(2**width-1 downto 0) of std_logic_vector(7 downto 0);
begin
[...]
end architecture;
The problem is "2**width". I currently worked around all power operators by inserting a constant before the type declaration.
3.1) I assume it's not intended to throw a bound error, nor to be a post VHDL-93 feature, is it?
Regards
Patrick
Wissenschaftliche Hilfskraft
Technische Universität Dresden
Fakultät Informatik
Institut für Technische Informatik
Lehrstuhl VLSI-Entwurfssysteme, Diagnostik und Architektur
01062 Dresden, GERMANY
Tel.: +49 351 463-38451 Fax: +49 351 463-38324
E-Mail: patrick.lehm...@tu-dresden.de
WWW: http://vlsi-eda.inf.tu-dresden.de
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