On 13/11/15 01:18, Lehmann, Patrick wrote:
Hello,
has anyone tried to compile the Altera (VHDL) libraries for GHDL?
I have tried, although not recently.
I found the complete simulation models in
"C:\Altera\15.0\quartus\library\sim_lib\..." as VHDL and Verilog files.
I tried to compile them but hit some problems:
1) Altera uses non standard IEEE packages, so I needed to configure GHDL
with -ieee=synopsys.
Yes.
1.1) Why is -ieee=mentor|synopsys not listed as a GHDL option anymore?
It is still displayed whith 'ghdl --help -a'
But I agree this should be displayed by default.
1.2) GHDL implecitely creates comparision operator(s) for
std_logic_vector in std_logic_1164.v93 (">=") which collides with
numeric_std.
I used -fexplicit as workaround, but is it correct behavior of GHDL to
generate a ">=" operator?
Yes.
2) One file has non ASCII chars (c) and TM in it - inserted in a comment
line. Nice new error message :).
They were not allowed at least in vhdl93 iirc. Try to add option -C.
I think I should write a bug report to Altera, because GHDL won't relax
on this rule, will it? ;)
What is your command line ?
3) There are dozens of bound errors complaining about bounds being no
universal integer or attribute. Example
entity foo is
generic (
Width : natural
)
[...]
end entity;
architecture rtl of foo is
type mem is array(2**width-1 downto 0) of std_logic_vector(7 downto 0);
begin
[...]
end architecture;
The problem is "2**width". I currently worked around all power operators
by inserting a constant before the type declaration.
Try -frelaxed-rules. Again, what is your command line ?
3.1) I assume it's not intended to throw a bound error, nor to be a post
VHDL-93 feature, is it?
No it is. The rule was relaxed in vhdl08. But I agree ghdl is too
conformant :-(
Regards,
Tristan.
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