On 13/11/15 11:36, Lehmann, Patrick wrote:
Hello,
to your answers:
2)
Using -C solved the multi-byte problem as expected.
2) and 3)
I added '-frelaxed-rules'. The libraries are now compiling.
The command line looks like this:
C:\Tools\GHDL\0.33\bin\ghdl.exe -a -P. --syn-binding -fexplicit --mb-comments
-frelaxed-rules --ieee=synopsys --std=93 --work=cycloneiv
C:\Altera\15.0\quartus\eda\sim_lib\cycloneiv_components.vhd
All your troubles come from using --std=93 instead of --std=93c !
Other observations:
==================================================================================
a) My script gives me these messages for 'cycloneiv_atoms.vhd':
command: C:\Tools\GHDL\0.33\bin\ghdl.exe -a -P. --syn-binding -fexplicit
--mb-comments -frelaxed-rules --ieee=synopsys --std=93 --work=cycloneiv
C:\Altera\15.0\quartus\eda\sim_lib\cycloneiv_atoms.vhd
ERROR while executing ghdl:
C:\Altera\15.0\quartus\eda\sim_lib\cycloneiv_atoms.vhd
Return Code: 1
--------------------------------------------------------------------------------
C:\Altera\15.0\quartus\eda\sim_lib\cycloneiv_atoms.vhd:2198:24:warning:
suspicious parenthesis around aggregate
C:\Altera\15.0\quartus\eda\sim_lib\cycloneiv_atoms.vhd:1064:9:warning: generic
"msgonchecks" is not a VITAL generic
C:\Altera\15.0\quartus\eda\sim_lib\cycloneiv_atoms.vhd:1065:9:warning: generic
"xonchecks" is not a VITAL generic
C:\Altera\15.0\quartus\eda\sim_lib\cycloneiv_atoms.vhd:1510:14:warning: generic
"lut_mask" is not a VITAL generic
C:\Altera\15.0\quartus\eda\sim_lib\cycloneiv_atoms.vhd:1511:14:warning: generic
"sum_lutc_input" is not a VITAL generic
C:\Altera\15.0\quartus\eda\sim_lib\cycloneiv_atoms.vhd:1512:15:warning: generic
"dont_touch" is not a VITAL generic
C:\Altera\15.0\quartus\eda\sim_lib\cycloneiv_atoms.vhd:1513:14:warning: generic
"lpm_type" is not a VITAL generic
C:\Altera\15.0\quartus\eda\sim_lib\cycloneiv_atoms.vhd:1517:14:warning: generic
"msgonchecks" is not a VITAL generic
C:\Altera\15.0\quartus\eda\sim_lib\cycloneiv_atoms.vhd:1518:14:warning: generic
"xonchecks" is not a VITAL generic
C:\Altera\15.0\quartus\eda\sim_lib\cycloneiv_atoms.vhd:1667:14:warning:
'datainglitch' is not a port name (in VITAL generic name)
C:\Altera\15.0\quartus\eda\sim_lib\cycloneiv_atoms.vhd:1738:14:warning: generic
"power_up" is not a VITAL generic
C:\Altera\15.0\quartus\eda\sim_lib\cycloneiv_atoms.vhd:1739:14:warning: generic
"x_on_violation" is not a VITAL generic
C:\Altera\15.0\quartus\eda\sim_lib\cycloneiv_atoms.vhd:1740:14:warning: generic
"lpm_type" is not a VITAL generic
C:\Altera\15.0\quartus\eda\sim_lib\cycloneiv_atoms.vhd:1766:14:warning: generic
"msgonchecks" is not a VITAL generic
C:\Altera\15.0\quartus\eda\sim_lib\cycloneiv_atoms.vhd:1767:14:warning: generic
"xonchecks" is not a VITAL generic
C:\Altera\15.0\quartus\eda\sim_lib\cycloneiv_atoms.vhd:2236:8: first
declaration must be the VITAL attribute specification
Is there an "error" string/text missing in the last line? Should it look like
this:
C:\Altera\15.0\quartus\eda\sim_lib\cycloneiv_atoms.vhd:2236:8:error: first
declaration must be the VITAL attribute specification
If so, I could scan the GHDL outputs for errors and warnings and colorize them
by a regexp :)
I think ghdl follows the gcc convention: messages are errors unless
prefixed by warning:.
Use --no-vital-check to remove vital checks.
===========================================================================
b) I have a 'component not bound' problem.
The files can be downloaded from GitHub (I don't want to spam the mailing list
with VHDL files):
ddrio.pkg.vhdl =>
https://github.com/VLSI-EDA/PoC/blob/master/src/io/ddrio/ddrio.pkg.vhdl
ddrio_in.vhdl =>
https://github.com/VLSI-EDA/PoC/blob/master/src/io/ddrio/ddrio_in.vhdl
ddrio_in_altera.vhdl =>
https://github.com/VLSI-EDA/PoC/blob/master/src/io/ddrio/ddrio_in_altera.vhdl
The entity ddrio_in is a wrapper for a Xilinx or Altera implementation. The
components are declared in ddrio.pkg.vhdl and
are used in ddrio_in.vhdl, but GHDL does not bind ddrio_in_altera to "i".
What am I doing wrong? I already experimented with the '--syn-binding' switch,
but no luck. The error is thrown when running
elaboration (-r) but not at analysis time (-a).
Yes, as binding is performed at elaboration.
Here is the log from my script (incl. compile order):
.....
command: C:\Tools\GHDL\0.33\bin\ghdl.exe -a -fexplicit -frelaxed-rules
--warn-binding --mb-comments --syn-binding -P. --ieee=synopsys --std=93
--work=poc D:\git\PoC\src\io\ddrio\ddrio.pkg.vhdl
command: C:\Tools\GHDL\0.33\bin\ghdl.exe -a -fexplicit -frelaxed-rules
--warn-binding --mb-comments --syn-binding -P. --ieee=synopsys --std=93
--work=poc D:\git\PoC\src\io\ddrio\ddrio_in_altera.vhdl
command: C:\Tools\GHDL\0.33\bin\ghdl.exe -a -fexplicit -frelaxed-rules
--warn-binding --mb-comments --syn-binding -P. --ieee=synopsys --std=93
--work=poc D:\git\PoC\src\io\ddrio\ddrio_in.vhdl
command: C:\Tools\GHDL\0.33\bin\ghdl.exe -a -fexplicit -frelaxed-rules
--warn-binding --mb-comments --syn-binding -P. --ieee=synopsys --std=93
--work=test D:\git\PoC\tb\io\ddrio\ddrio_in_tb.vhdl
running simulation...
command: C:\Tools\GHDL\0.33\bin\ghdl.exe -r -P. --std=93 --syn-binding
--work=test ddrio_in_tb
ghdl messages for : D:\git\PoC\tb\io\ddrio\ddrio_in_tb.vhdl
--------------------------------------------------------------------------------
D:\git\PoC\src\io\ddrio\ddrio_in.vhdl:84:16:warning: 'i' is not bound
D:\git\PoC\src\io\ddrio\ddrio_in.vhdl:76:14:warning: (in default configuration
of ddrio_in(rtl))
Possible error message improvement: the instance label "i" is used twice in the
code. Once for genAltera and once for genXilinx.
Is it possible to report the full instance path for the unbound object?
Doesn't line number help ?
I will have a look at the sources.
Tristan.
Example:
D:\git\PoC\src\io\ddrio\ddrio_in.vhdl:84:16:warning: 'genAltera.i' is not bound
Regards
Patrick
-----------------------------------
Wissenschaftliche Hilfskraft
Technische Universität Dresden
Fakultät Informatik
Institut für Technische Informatik
Lehrstuhl VLSI-Entwurfssysteme, Diagnostik und Architektur
01062 Dresden
Tel.: +49 351 463-38451
Fax: +49 351 463-38324
Raum: APB-1020
E-Mail: patrick.lehm...@tu-dresden.de
WWW: http://vlsi-eda.inf.tu-dresden.de
-----Original Message-----
From: Ghdl-discuss [mailto:ghdl-discuss-boun...@gna.org] On Behalf Of Tristan
Gingold
Sent: Friday, November 13, 2015 5:20 AM
To: ghdl-discuss@gna.org
Subject: Re: [Ghdl-discuss] Compiling Altera libraries for GHDL
On 13/11/15 01:18, Lehmann, Patrick wrote:
Hello,
has anyone tried to compile the Altera (VHDL) libraries for GHDL?
I have tried, although not recently.
I found the complete simulation models in
"C:\Altera\15.0\quartus\library\sim_lib\..." as VHDL and Verilog files.
I tried to compile them but hit some problems:
1) Altera uses non standard IEEE packages, so I needed to configure
GHDL with -ieee=synopsys.
Yes.
1.1) Why is -ieee=mentor|synopsys not listed as a GHDL option anymore?
It is still displayed whith 'ghdl --help -a'
But I agree this should be displayed by default.
1.2) GHDL implecitely creates comparision operator(s) for
std_logic_vector in std_logic_1164.v93 (">=") which collides with
numeric_std.
I used -fexplicit as workaround, but is it correct behavior of GHDL to
generate a ">=" operator?
Yes.
2) One file has non ASCII chars (c) and TM in it - inserted in a
comment line. Nice new error message :).
They were not allowed at least in vhdl93 iirc. Try to add option -C.
I think I should write a bug report to Altera, because GHDL won't
relax on this rule, will it? ;)
What is your command line ?
3) There are dozens of bound errors complaining about bounds being no
universal integer or attribute. Example
entity foo is
generic (
Width : natural
)
[...]
end entity;
architecture rtl of foo is
type mem is array(2**width-1 downto 0) of std_logic_vector(7
downto 0); begin [...] end architecture;
The problem is "2**width". I currently worked around all power
operators by inserting a constant before the type declaration.
Try -frelaxed-rules. Again, what is your command line ?
3.1) I assume it's not intended to throw a bound error, nor to be a
post
VHDL-93 feature, is it?
No it is. The rule was relaxed in vhdl08. But I agree ghdl is too conformant
:-(
Regards,
Tristan.
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