I was told (years ago,different hardware) that the pipeline was filled with the appropriate number of NOPs. Might have just been an engineer finding a convenient explanation for a sysprog though ...
I always wondered how that worked across different workloads - with all the smarts built into the hardware to optimize overlapped pipeline stages and branch prediction. No doubt a better answer will arise. Shane ... On Wed, Mar 3rd, 2010 at 8:59 AM, "McKown, John" <john.mck...@healthmarkets.com> wrote: > There are multiple z9 "models". Each model has its own MSU rating, > which is basically related to the number of CPs enabled and their > "speed". Now, I know that all the CPs on all z9 run same hardware > speed. So, I'm wondering how they are "knee capped"? Now, I know that > the "knee capping" is done by loading in a specific MCL. So, I'm > thinking that this somehow does something like "inserts a wait state" > during instruction processing. That is, the XYZ instruction on all > z9s run in the same amount of time. But there is "something extra" > done at the end of the XYZ instruction which causes a "wait" before > the next instruction is actually executed. Am I on the right track? > Or is it done is some other strange manner? ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the message: GET IBM-MAIN INFO Search the archives at http://bama.ua.edu/archives/ibm-main.html
