McKown, John wrote:
There are multiple z9 "models". Each model has its own MSU rating, which is basically related to the number of CPs enabled and their "speed". Now, I know that all the CPs on all z9 run same hardware speed. So, I'm wondering how they are "knee capped"? Now, I know that the "knee capping" is done by loading in a specific MCL. So, I'm thinking that this somehow does something like "inserts a wait state" during instruction processing. That is, the XYZ instruction on all z9s run in the same amount of time. But there is "something extra" done at the end of the XYZ instruction which causes a "wait" before the next instruction is actually executed. Am I on the right track? Or is it done is some other strange manner?
There is a hardware timer pop (think STIMER REAL) that occurs every 'n' milliseconds on every CP that passes control to a millicode routine that does important housekeeping tasks for the CP, such as noticing and responding to SIGP requests. Before exiting this routine, they load a model-dependent integer value into a millicode register (Rx) and execute BCT Rx,* which "chews" up the prescribed amount of processor cycles.
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