This is simply incredible, to think that IBM would deliberately run BCT
loops to throttle, slowdown, CPs.

It is one thing to cut back the CPU cache.  It is quite another to
deliberate slow things down.

When will they ever learn that quality sells more than anything else and
that making anything less than the best possible product just hurts
themselves.

Detroit is in shambles because of "built-in obsolescence".

My 1997 Honda Civic with the original radiator, air conditioner, heater
coil, starter, fuel pump, gas tank, etc has 374,000 miles on it and about
the only thing I have ever had to replace, aside from regular wear and tear
like tires, muffler, brakes, battery etc, is the ignition coil.

Sakichi Toyoda, (1867-1930) the greatest inventor and industrialist of
Japan, built his company in the early 1900's which later spawned the current
Toyota auto company, currently the world's largest automobile company,
despite recent problems.

BTW: the name Toyoda was changed to Toyota for PR reasons; the former has
bad connotations in Japanese.

Sakichi Toyoda, built is company and success on what is know as the 5 Whys.

When doing PD he required his people to ask a minimum of 5 Whys to get at
the root cause of the problem:

My car will not start. (the problem)

   1. *Why?* - The battery is dead. (first why)
   2. *Why?* - The alternator is not functioning. (second why)
   3. *Why?* - The alternator belt has broken. (third why)
   4. *Why?* - The alternator belt was well beyond its useful service life
   and has never been replaced. (fourth why)
   5. *Why?* - I have not been maintaining my car according to the
   recommended service schedule. (fifth why, a root cause)

The current trend towards CMMI and the Six Sigma standard of quality, 6
standard deviations (3.4 defects in a million) instead of the typical 3
standards deviations (1 defect in 370) points to the demand for quality,
excellence,  and perfection in everything.

No one will settle for less.

It is only a question of time before IBM goes the way of Detroit, if they do
not wake up.

On Wed, Mar 3, 2010 at 4:03 AM, Edward Jaffe <edja...@phoenixsoftware.com>wrote:

> McKown, John wrote:
>
>> There are multiple z9 "models". Each model has its own MSU rating, which
>> is basically related to the number of CPs enabled and their "speed". Now, I
>> know that all the CPs on all z9 run same hardware speed. So, I'm wondering
>> how they are "knee capped"? Now, I know that the "knee capping" is done by
>> loading in a specific MCL. So, I'm thinking that this somehow does something
>> like "inserts a wait state" during instruction processing. That is, the XYZ
>> instruction on all z9s run in the same amount of time. But there is
>> "something extra" done at the end of the XYZ instruction which causes a
>> "wait" before the next instruction is actually executed. Am I on the right
>> track? Or is it done is some other strange manner?
>>
>>
>
> There is a hardware timer pop (think STIMER REAL) that occurs every 'n'
> milliseconds on every CP that passes control to a millicode routine that
> does important housekeeping tasks for the CP, such as noticing and
> responding to SIGP requests. Before exiting this routine, they load a
> model-dependent integer value into a millicode register (Rx) and execute BCT
> Rx,* which "chews" up the prescribed amount of processor cycles.
>
> --
> Edward E Jaffe
> Phoenix Software International, Inc
> 831 Parkview Drive North
> El Segundo, CA 90245
> 310-338-0400 x318
> edja...@phoenixsoftware.com
> http://www.phoenixsoftware.com/
>
>
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-- 
George Henke
(C) 845 401 5614

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