I was really "excited" by the "conditional load/store" which I guess is similar to the compare and branch instructions. I don't know if they will combine a "compare and load/store" or do a load/store based on the existing CC from a previous instruction. I remember a RISC processor of some sort where every instruction was conditional. On the z, that would cost 4 bits per instruction if the mask were encoded like in a branch. I wonder how that would affect efficiency and pipelining?
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