[email protected] (Tom Marchant) writes:
> Bold assertion.  Do you have any data to back that up?

360 allowed self-modifying instruction ... potentially instructions
already in the pipeline. one of the claims for Amdahl "macro-code" was
that it was essentially 370 with some tweaks ... including precluding
self-modifying. even in some number of (non-cache, non-pipeline) 360s
that did i-fetch a double word (or more at time) ... there was extra
overhead in constantly checking whether there was storage alteration to
address that was already fetched by the instruction unit (within the
same double word).

"harvard" architectures with split instruction and data caches w/o cache
concistency ....  get some processing performance by i-cache ignoring
standard storage alterations. in the case of "store-in" data cache
... program loaders that may operate on instruction streams ... making
alterations that appear in d-cache. before initiating exection ... the
loader then executes special operation that explicitly forces d-cache
alterated lines to main storage and invalidates possible corresponding
i-cache lines. with the force of altered data (from d-cache) to storage
and invalidation of corresponding addresses in i-cache ... subsequent
instruction stream references to those addressed would be forced to
fetch the contents from storage (explicit programming required to
support alteration of potential instructions).

"harvard" architecture with i-cache operation ignoring standard storage
alterations ... is much easier to pipeline and easier to scaleup
multiprocessor (not only being able to ignore storage alterations on the
same processor ... but also able to ignore standard storage alterations
on all the other processors).

-- 
virtualization experience starting Jan1968, online at home since Mar1970

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