On Thu, 27 Jul 2006 17:21:00 +0000 "Jeffrey D. Smith"
<[EMAIL PROTECTED]> wrote:

:>From: "Binyamin Dissen" <[EMAIL PROTECTED]>
:>Sent: 7/27/2006 10:22 AM
:>To: "IBM-MAIN@BAMA.UA.EDU" <IBM-MAIN@BAMA.UA.EDU>
:>Subject: Re: Doing a LM of two words on a double word bounday - is it 
serialized?

:>On Thu, 27 Jul 2006 15:54:00 +0000 "Jeffrey D. Smith"
:><[EMAIL PROTECTED]> wrote:

:>:>LM  R2,R3,operand    ; no check-point synch, no store.

:>:>will concurrently load R2,R3. The values are fetched 8-bytes
:>:>in parallel. If another CPU is concurrently storing 8-bytes,
:>:>then your CPU will see the entire old 8-bytes or the entire
:>:>new 8-bytes and never a mixture of old and new bytes.

:>:>Note that if another CPU is storing with a narrower alignment,
:>:>like a 4-byte store, then you will get inconsistent results
:>:>with either CDS or LM/STM.

:>In other words, if CPU1 is doing the LM of the doubleword while CPU2 is using
:>PLO changing the two words via CSST (each separately on a word boundary), it
:>is undefined whether CPU1 will get a consistent answer?

:>I was thinking of using one word as a update-counter and the other a pointer
:>to the chain.

:>I was going to use PLO to do a compare/swap/store, with the compare/swap on
:>the count and a store into the chain (possibly into the head pointer - thus
:>both words in the doubleword would be accessed as single words). Obviously I
:>would get bad results if the load of the chain header/count did not get a
:>consistent result.

:>Load word1 followed by PLO CL would obviously get consistent results.

:>All CPUs that are fetching/storing must use the same alignment
:>and the same serialization mechanism. For updating, they must
:>all use CS/CDS/CSG/CDSG, or they must all use PLO with R1 pointing
:>at the same lock token (I just use the list header address for R1).

:>PLO is designed for discontiguous fetch/store. If it just happens
:>that two words are adjacent in the same double word, that won't
:>assure an 8-byte concurrent store as viewed by other CPU. It will
:>look like two 4-byte concurrent stores separated in time. The PLO
:>compare-swap-single/double/triple-store performs the compare
:>first and the swap last. All of the accesses performed by PLO
:>appear to other CPU to be separated in time. PLO simply uses a
:>"red light/green light" hardware semaphore to delay other CPU
:>(also using PLO) from accessing the operands.

In other words, are you saying in the case above that the LM can get
inconsistent results? That L/PLO-CL is required?

--
Binyamin Dissen <[EMAIL PROTECTED]>
http://www.dissensoftware.com

Director, Dissen Software, Bar & Grill - Israel


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