The following message is a courtesy copy of an article that has been posted to bit.listserv.ibm-main,alt.folklore.computers as well.
[EMAIL PROTECTED] writes: > This has always intrigued me. What was done to eliminate the > possibility that the channel had to access a virtual page that had > been paged out? An enabled application or system code that is copying > and translating virtual-to-real addresses can always suffer a page > fault, wait for the page-in, and resume as if nothing had happened, > but channels cannot wait for page-fault resolution. Or could they? re: http://www.garlic.com/~lynn/2007p.html#69 GETMAIN/FREEMAIN and virtual storage backing up part of CCWTRANS creation of "shadow" channel programs (with real addresses) included pinning/locking the associated virtual pages (to those real-addresses). after the real i/o had completed (running with the "shadow" channel program), there was an UNTRANS process ... that included unpinning the associated virtual pages. the original 370 virutal memory architecture included some number of features that didn't actually make it out. i've posted before about some features that the 165 hardware engineers ran into problems ... creating full 370 virtual memory hardware retrofit to the 165 ... and in escalation where they claimed they could pickup six months on the delivery schedule if they could drop the features ... and the pok favorite son operating system expressed they could see no use for the features. dropping the features then met that all the other processors had to undo their implementation and any software that was already completed that would use the additional features ... and to be reworked. there had been channel operation with virtual addresses defined (including being able to suspend because of a page-fault and then be resumed) and there was folklore there was even patents on such channel operation with virtual addresses. this never got very far into the 370 architecture. for lots of topic drift ... past posts mentioning issue with 370/165 virtual memory hardware retrofit schedule and dropping a number of features to make up six monhts http://www.garlic.com/~lynn/95.html#3 What is an IBM 137/148 ??? http://www.garlic.com/~lynn/99.html#7 IBM S/360 http://www.garlic.com/~lynn/99.html#204 Core (word usage) was anti-equipment etc http://www.garlic.com/~lynn/99.html#209 Core (word usage) was anti-equipment etc http://www.garlic.com/~lynn/2000d.html#82 "all-out" vs less aggressive designs (was: Re: 36 to 32 bit transition) http://www.garlic.com/~lynn/2000f.html#35 Why IBM use 31 bit addressing not 32 bit? http://www.garlic.com/~lynn/2000f.html#55 X86 ultimate CISC? No. (was: Re: "all-out" vs less aggressive designs) http://www.garlic.com/~lynn/2000f.html#63 TSS ancient history, was X86 ultimate CISC? designs) http://www.garlic.com/~lynn/2000g.html#10 360/370 instruction cycle time http://www.garlic.com/~lynn/2000g.html#15 360/370 instruction cycle time http://www.garlic.com/~lynn/2000g.html#16 360/370 instruction cycle time http://www.garlic.com/~lynn/2000g.html#21 360/370 instruction cycle time http://www.garlic.com/~lynn/2001.html#63 Are the L1 and L2 caches flushed on a page fault ? http://www.garlic.com/~lynn/2001b.html#37 John Mashey's greatest hits http://www.garlic.com/~lynn/2001k.html#8 Minimalist design (was Re: Parity - why even or odd) http://www.garlic.com/~lynn/2002.html#48 Microcode? http://www.garlic.com/~lynn/2002.html#50 Microcode? http://www.garlic.com/~lynn/2002.html#52 Microcode? http://www.garlic.com/~lynn/2002g.html#47 Why are Mainframe Computers really still in use at all? http://www.garlic.com/~lynn/2002l.html#51 Handling variable page sizes? http://www.garlic.com/~lynn/2002m.html#2 Handling variable page sizes? http://www.garlic.com/~lynn/2002m.html#68 Tweaking old computers? http://www.garlic.com/~lynn/2002n.html#10 Coherent TLBs http://www.garlic.com/~lynn/2002n.html#15 Tweaking old computers? http://www.garlic.com/~lynn/2002n.html#23 Tweaking old computers? http://www.garlic.com/~lynn/2002n.html#32 why does wait state exist? http://www.garlic.com/~lynn/2002n.html#58 IBM S/370-168, 195, and 3033 http://www.garlic.com/~lynn/2002p.html#44 Linux paging http://www.garlic.com/~lynn/2003e.html#12 Resolved: There Are No Programs With >32 Bits of Text http://www.garlic.com/~lynn/2003f.html#56 ECPS:VM DISPx instructions http://www.garlic.com/~lynn/2003g.html#19 Multiple layers of virtual address translation http://www.garlic.com/~lynn/2003g.html#20 price ov IBM virtual address box?? http://www.garlic.com/~lynn/2003h.html#37 Does PowerPC 970 has Tagged TLBs (Address Space Identifiers) http://www.garlic.com/~lynn/2003m.html#34 SR 15,15 was: IEFBR14 Problems http://www.garlic.com/~lynn/2003m.html#37 S/360 undocumented instructions? http://www.garlic.com/~lynn/2004c.html#6 If the x86 ISA could be redone http://www.garlic.com/~lynn/2004p.html#8 vm/370 smp support and shared segment protection hack http://www.garlic.com/~lynn/2005b.html#53 The mid-seventies SHARE survey http://www.garlic.com/~lynn/2005b.html#62 The mid-seventies SHARE survey http://www.garlic.com/~lynn/2005e.html#53 System/360; Hardwired vs. Microcoded http://www.garlic.com/~lynn/2005e.html#57 System/360; Hardwired vs. Microcoded http://www.garlic.com/~lynn/2005e.html#59 System/360; Hardwired vs. Microcoded http://www.garlic.com/~lynn/2005f.html#1 System/360; Hardwired vs. Microcoded http://www.garlic.com/~lynn/2005f.html#45 Moving assembler programs above the line http://www.garlic.com/~lynn/2005g.html#17 DOS/360: Forty years http://www.garlic.com/~lynn/2005h.html#10 Exceptions at basic block boundaries http://www.garlic.com/~lynn/2005h.html#18 Exceptions at basic block boundaries http://www.garlic.com/~lynn/2005j.html#39 A second look at memory access alignment http://www.garlic.com/~lynn/2005p.html#45 HASP/ASP JES/JES2/JES3 http://www.garlic.com/~lynn/2005r.html#51 winscape? http://www.garlic.com/~lynn/2005s.html#23 winscape? http://www.garlic.com/~lynn/2006.html#13 VM maclib reference http://www.garlic.com/~lynn/2006.html#38 Is VIO mandatory? http://www.garlic.com/~lynn/2006e.html#0 About TLB in lower-level caches http://www.garlic.com/~lynn/2006e.html#5 About TLB in lower-level caches http://www.garlic.com/~lynn/2006e.html#12 About TLB in lower-level caches http://www.garlic.com/~lynn/2006e.html#46 using 3390 mod-9s http://www.garlic.com/~lynn/2006i.html#4 Mainframe vs. xSeries http://www.garlic.com/~lynn/2006i.html#9 Hadware Support for Protection Bits: what does it really mean? http://www.garlic.com/~lynn/2006i.html#23 Virtual memory implementation in S/370 http://www.garlic.com/~lynn/2006j.html#5 virtual memory http://www.garlic.com/~lynn/2006j.html#31 virtual memory http://www.garlic.com/~lynn/2006j.html#41 virtual memory http://www.garlic.com/~lynn/2006k.html#57 virtual memory http://www.garlic.com/~lynn/2006l.html#22 Virtual Virtualizers http://www.garlic.com/~lynn/2006m.html#26 Mainframe Limericks http://www.garlic.com/~lynn/2006n.html#16 On the 370/165 and the 360/85 http://www.garlic.com/~lynn/2006r.html#36 REAL memory column in SDSF http://www.garlic.com/~lynn/2006s.html#30 Why magnetic drums was/are worse than disks ? http://www.garlic.com/~lynn/2006s.html#61 Is the teaching of non-reentrant HLASM coding practices ever defensible? http://www.garlic.com/~lynn/2006t.html#1 Is the teaching of non-reentrant HLASM coding practices ever http://www.garlic.com/~lynn/2006u.html#60 Why these original FORTRAN quirks? http://www.garlic.com/~lynn/2006y.html#26 moving on http://www.garlic.com/~lynn/2006y.html#35 The Future of CPUs: What's After Multi-Core? http://www.garlic.com/~lynn/2006y.html#40 Multiple mappings http://www.garlic.com/~lynn/2007d.html#32 Running OS/390 on z9 BC http://www.garlic.com/~lynn/2007f.html#7 IBM S/360 series operating systems history http://www.garlic.com/~lynn/2007f.html#14 more shared segment archeology http://www.garlic.com/~lynn/2007f.html#16 more shared segment archeology http://www.garlic.com/~lynn/2007g.html#72 The Perfect Computer - 36 bits? http://www.garlic.com/~lynn/2007j.html#43 z/VM usability http://www.garlic.com/~lynn/2007k.html#28 IBM 360 Model 20 Questions http://www.garlic.com/~lynn/2007n.html#35 IBM obsoleting mainframe hardware http://www.garlic.com/~lynn/2007o.html#26 Tom's Hdw review of SSDs http://www.garlic.com/~lynn/2007o.html#41 Virtual Storage implementation http://www.garlic.com/~lynn/2007o.html#53 Virtual Storage implementation ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [EMAIL PROTECTED] with the message: GET IBM-MAIN INFO Search the archives at http://bama.ua.edu/archives/ibm-main.html
