Clark,

I seriously doubt COBOL is on a deathbed considering how java performs on a 
z/os.
Secondly, a serious amount of banking is on legacy machines in COBOL. 
Banks aren't going to convert if it costs more money

Scott ford
www.identityforge.com

On Aug 31, 2012, at 7:39 PM, Clark Morris <cfmpub...@ns.sympatico.ca> wrote:

> On 28 Aug 2012 06:55:54 -0700, in bit.listserv.ibm-main you wrote:
> 
>> With the new machine,it seems like there is  A LOT  to read which is greate! 
>> .. You may find it usefull to check  this part of Draft EC12 tech guide 
>> redbook.I  think it is nice,because it summaries performance items well ....
> 
> I notice that the language most used on the z, COBOL has NO
> improvements related to the EC12.  There are improvements for PL/1 and
> C/C++.  This speaks louder than anything else as to whether IBM thinks
> COBOL is on its deathbed.
> 
> Clark Morris
>> 
>> Regards
>> Meral
>> 
>> 1.9.7 Main performance improvement drivers with zEC12
>> 
>> The zEC12 is designed to deliver new levels of performance and capacity for 
>> large scale
>> consolidation and growth. The following attributes and design points of the 
>> zEC12 contribute
>> to overall performance and throughput improvements as compared to the z196.
>> /Architecture implementation enhancements:
>> 
> Transactional Execution (TX) designed for z/OS, Java, DB2 and other
> exploiters
>> 
> Runtime Instrumentation (RI) provides dynamic and self-tuning online
> re-compilation
>> capability for Java workloads
>> 
> Enhanced DAT-2 for supporting 2 GB large pages for DB2 buffer pools,
> Java heap size and
>> other large structures
>> 
> Software directives implementation to improve hardware performance
>> 
> Decimal format conversions for COBOL programs.
>> zEC12 microprocessor design enhancements:
>> 
> Six processor cores per chip
>> 
> Enhanced Out Of Order (OOO) execution design
>> 
> Improved pipeline balance
>> 
> Enhanced branch prediction latency and instruction fetch throughput
>> 
> Improvements on execution bandwidth and throughput
>> 
> New design for Level 2 private cache with separation of cache
> structures for instructions
>> and L2 operands
>> 
> Reduced access latency for most of Level 1 cache misses
>> 
> Bigger Level 2 cache with shorter latency
>> 
> Third level on-chip shared cache is doubled
>> 
> Fourth level book-shared cache is doubled
>> 
> Hardware and software prefetcher handling improvements
>> 
> Increased execution/completion throughput
>> 
> Improve fetch and store conflict scheme
>> 
> Enhance branch prediction structure and sequential instruction
> fetching
>> 
> Millicode performance improvements
>> 
> Optimized floating-point performance
>> 
> Faster engine for fixed-point division
>> 
> New second level branch prediction array
>> 
> One cryptographic/compression co-processor per core
>> 
> Cryptography support of UTF8<>UTF16 conversions
>> 
> Higher clock frequency at 5.5 GHz
>> 
> IBM CMOS 13S 32nm SOI technology with IBM eDRAM technology.
>> zEC12 design enhancements:
>> 
> Increased total number of PUs available on the system, from 96 to
> 120, and number of
>> characterizable cores, from 80 to 101
>> 
> Hardware System Area increased from 16 GB to 32 GB
>> 
> Increased default number of SAP processors per book
>> 
> New CFCC code available for improved performance
>> – Elapsed time improvements when dynamically altering the size of a cache 
>> structure
>> – DB2 conditional write to a group buffer pool (GBP)
>> – Performance improvements for coupling facility cache structures to avoid 
>> flooding the
>> coupling facility cache with changed data and avoid excessive delays and 
>> backlogs for
>> cast-out processing
>> – Performance throughput enhancements for parallel cache castout processing 
>> by
>> extending the number of RCC cursors beyond 512
>> – CF Storage class and castout class contention avoidance by breaking up 
>> individual
>> storage class and castout class queues to reduce storage class and castout 
>> class latch
>> contention.
>> New features available on the zEC12:
>> 
> Crypto Express4S performance enhancements
>> 
> Flash Express PCIe cards to handle paging workload spikes and improve
> performance
>> 
>> 
>> 
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