By the way, I just wanted to say that I REALLY ENJOY these sorts of conversations (technical ones) on this list.
The obnoxious sniping we are seeing between some of our members needs to stop. I don't understand why the moderators let it continue. If it were me, the folks doing the sniping would be removed from the list fairly quickly. Anyway, a "thank you" to Joe for bringing up this interesting topic, and to all the folks who have chimed in (especially gil and Peter who both brought up some great points and some confusing phrasing in the pubs that IBM should fix). > From: "Paul Gilmartin" <0000000433f07816-dmarc-requ...@listserv.ua.edu> > > On Sun, 24 Oct 2021 08:55:00 -0400, Peter Relson wrote: > >For CPU table entries that are addressed by real or absolute addresses, it > >is unpredictable > >whether the address wraps or an addressing exception is recognized. > > Does "unpredictable whether the address wraps" imply that in AMODE 31 > the sign bit might be set to 1, or that in AMODE 24 the leftmost octet > might be set other than to x'00'? Given how we write the architecture on System z, it means exactly what it says: "unpredictable". It WOULD be deterministic for a given CPU but we make not promises across multiple generations of CPU. We (IBM) are constantly trying to improve performance for common cases, which is why PoPs claims unpredictability for cases that no reasonable program should generate. > Paul G wrote: > I stand by my assertion: > On Sat, 23 Oct 2021 20:32:41 -0500, Paul Gilmartin wrote: > > ... > >An exception is *never* recognized on an LA instruction, even > though wraparound > >might occur or the value before truncation exceeds 24, 32, or 64 bits. I agree with this assertion but not your statement that: > >An interrupt condition is *never* recognized "during generation of [an] > >address." Sorry if that wasn't clear. I purposely snipped quite a bit of the documentation as I was trying to answer the original question about whether index registers are signed (they are not) and WHY using a 2s complement format in an unsigned 64-bit field actually works even though it's not really documented that way (address wraparound). > >(I don't know exactly what a "CPU table entry" is in this context.) > > > I readily suspect that the writer knew no better than you and merely > supplied the output off a Travesty Generator. I thing the Travesty Generator statement is a bit too much. My guess as to what happened: Our pubs writers tried really hard to make things clear but in trying to edit the technical details, they slightly mixed them up or left out some details that would have clarified. I do agree that you should submit an RCF to get that section cleared up. When none of the multiple technical folks reading a definitive source (Principles of Operations) don't understand what something means in a given context, that says it really needs to be made clearer. Eric Rossman ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
