Where registers are stored depends on the type of interrupt, and there are five types, not just two.
In the case of a program check*, what happens depends on the type, state and whether it is covered by a match [E]SPIE. In the case of a program check resulting in an S0Cx or S0Dx ABEND, the PSW is stored in the failing RB and the general registers are stored in the new ABEND SVRB. * ABEND S0C4 is not a program check. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר ________________________________________ From: IBM Mainframe Discussion List <IBM-MAIN@LISTSERV.UA.EDU> on behalf of Joseph Reichman <reichman...@gmail.com> Sent: Saturday, February 3, 2024 8:20 PM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Registers in the RB It was my understanding probably erroneously that when a RB I guess I am talking about a PRB gets interrupted and that can happen in one of two instances 1) An SVC 2) A Program check e.g. S0C1,4, Then if the interrupt is because of an SVC the program registers will be saved in the new SVRB if it's because of the program check then it will be saved in that RB Just was looking at my abended rb in SDWARBAD which took off via a synch macro and I deliberately abended it with a s0c1 the RBOPSW matched SDWAEC1 However the registers were in the next RB If anyone can clarify this issue I would be very grateful thanks ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
