That for all interrupts PSW and CDE if one exits is in old register in new 

Thanks 

> On Feb 4, 2024, at 6:40 PM, Seymour J Metz <sme...@gmu.edu> wrote:
> 
> Yes, general registers go in the new RB, PSW in the old. Whent the task is 
> not running the newest RB holds the PSW and the TCB holds the general 
> registers. I havent checked how the top halves are handled.
> 
> --
> Shmuel (Seymour J.) Metz
> http://mason.gmu.edu/~smetz3
> עַם יִשְׂרָאֵל חַי
> נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר
> 
> ________________________________________
> From: IBM Mainframe Discussion List <IBM-MAIN@LISTSERV.UA.EDU> on behalf of 
> Joseph Reichman <reichman...@gmail.com>
> Sent: Sunday, February 4, 2024 12:53 PM
> To: IBM-MAIN@LISTSERV.UA.EDU
> Subject: Re: Registers in the RB
> 
> And they are in the manual you previously
> 
> Posted ?
> 
> 
> Just for clarity sake
> 
> Just ran  a small test
> 
> For the interrupt PSW which in the case of some PRB s might have a cde
> 
> The registers that go along with that RBOPSW
> Are always in the next rb
> 
> Regardless of the cause of the interrupt
> 
> Hope this is right
> 
> Thank you very much all
> 
>> On Feb 4, 2024, at 11:49 AM, Seymour J Metz <sme...@gmu.edu> wrote:
>> 
>> Yes, expressed in hexadecimal. Systems Codes has a complete list of program 
>> interrupt codes that can cause an S0C4 if not intercepted.
>> 
>> --
>> Shmuel (Seymour J.) Metz
>> http://mason.gmu.edu/~smetz3
>> עַם יִשְׂרָאֵל חַי
>> נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר
>> 
>> ________________________________________
>> From: IBM Mainframe Discussion List <IBM-MAIN@LISTSERV.UA.EDU> on behalf of 
>> Joseph Reichman <reichman...@gmail.com>
>> Sent: Sunday, February 4, 2024 11:45 AM
>> To: IBM-MAIN@LISTSERV.UA.EDU
>> Subject: Re: Registers in the RB
>> 
>> 
>> Seymour
>> 
>> When you say for example IC10 you are referring what would be in RBINTCOD 
>> correct ?
>> 
>>>> On Feb 4, 2024, at 11:33 AM, Seymour J Metz <sme...@gmu.edu> wrote:
>>> Since OS/VS, interrupt code 04 is less common amd an S0C4 is more likely 
>>> to be due to e.g., IC10, IC11. In MVT it's always IC04.
>>> 
>>> --
>>> Shmuel (Seymour J.) Metz
>>> http://mason.gmu.edu/~smetz3
>>> עַם יִשְׂרָאֵל חַי
>>> נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר
>>> 
>>> ________________________________________
>>> From: IBM Mainframe Discussion List <IBM-MAIN@LISTSERV.UA.EDU> on behalf of 
>>> Joseph Reichman <reichman...@gmail.com>
>>> Sent: Sunday, February 4, 2024 11:11 AM
>>> To: IBM-MAIN@LISTSERV.UA.EDU
>>> Subject: Re: Registers in the RB
>>> 
>>> I’m trying to understand so that u don’t mess things up
>>> 
>>> The way Seymour explained it
>>> 
>>> For purposes of example the hardware gives control to the program check
>>> FLIH for interrupt code 4 the program check FLIH issues ABEND abend code
>>> 0C4 reason 4
>>> 
>>> Joe Reichman
>>> 
>>> 
>>>> On Sun, Feb 4, 2024 at 11:06 AM Binyamin Dissen 
>>>> <bdis...@dissensoftware.com>
>>>> wrote:
>>>> 
>>>> On Sun, 4 Feb 2024 10:29:59 -0500 Joseph Reichman <reichman...@gmail.com>
>>>> wrote:
>>>> 
>>>> :>But thought S0C4 is a program check
>>>> 
>>>> It is.
>>>> 
>>>> It may be a pic-4,-10, or -11. If PIC-4, PSW was updated.
>>>> 
>>>> An error recovery routine that messes up things is worse than none.
>>>> 
>>>> --
>>>> Binyamin Dissen <bdis...@dissensoftware.com>
>>>> http://secure-web.cisco.com/1816mdJ8h5-_oO1Xw58w3a8lEY_-kExorCz4aYg_qWRPUg_S6L1Z7PSPpA_kZcoVdyWJRO7o8CZk3cdmof4xYFKWUq5F_354st8NqQ1H-DfhXLX7hOZMR91CjoL1YT6Mbzl6njAZmKFdodaka0a1fK4YYTFZC0MgMlnj3ZJIgBM_AqiHoqGC_AbIMpQH0IAacZQAZlVgvJf80mITj1INV2l7F5k_pFjt0QOTQKtvKl1ATyTUInntV2lYhaRLgGmYZAWVJIDYXYDUZJUKOWAxwAMDRvCZ_zlmMheKUwEgmhUqjkH-LZSn6EJ0dT3AX1KtXJ7SEVz6_Ju0n0gr_1s7lMc-k6E1u0vGItaEOADznerc8n-GIWT-wkJUZtCSSs1yckiVlCN-FkVRjnrgwLsd35OJUqktorRcnmAbG4EHP89E/http%3A%2F%2Fwww.dissensoftware.com
>>>> 
>>>> Director, Dissen Software, Bar & Grill - Israel
>>>> 
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