On 6/2/2014 9:06 AM, Paul Gilmartin wrote:
On Mon, 2 Jun 2014 11:47:17 -0400, John Eells wrote:
The caches are divided into 256-byte increments called "cache lines" in
current processors.
(The exact number is probably subject to change.)
Modern processors implement instructions a program can use to learn
about the cache configuration on the machine, though I don't expect the
line size to change in my lifetime.
Does HLASM and/or STORAGE provide for cache line alignment?
For a long, long time now...
I've long wondered why the NIL and OIL macros are necessary to
lock access to bits within a byte, whereas the hardware performs
the equivalent function for bytes within a cache line.
NIL and OIL are not required on z196 and higher machines. NI and OI now
do the necessary serialization.
--
Edward E Jaffe
Phoenix Software International, Inc
831 Parkview Drive North
El Segundo, CA 90245
http://www.phoenixsoftware.com/
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