Hi Phil, I would consider something like this:
LR R15,R3 Copy low 32-bits to R15 SRLG R0,R3,32 Copy upper 32-bits to R0 You may want to add an SR or XR for register 0 and 15 prior to the above two instructions if you want to make sure of the upper 32-bits of the target registers. Chuck Charles (Chuck) Hardee Senior Systems Engineer/Database Administration EAS Information Technology Thermo Fisher Scientific 300 Industry Drive | Pittsburgh, PA 15275 Phone +1 (724) 517-2633 | Mobile +1 (412) 877-2809 | FAX: +1 (412) 490-9230 chuck.har...@thermofisher.com | www.thermofisher.com WORLDWIDE CONFIDENTIALITY NOTE: Dissemination, distribution or copying of this e-mail or the information herein by anyone other than the intended recipient, or an employee or agent of a system responsible for delivering the message to the intended recipient, is prohibited. If you are not the intended recipient, please inform the sender and delete all copies. -----Original Message----- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf Of Phil Smith III Sent: Thursday, June 23, 2016 5:51 PM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Simple assembler question With all of the 273 new formats of LOAD, I assume this is hiding in there somewhere: I have a value in grande register 3. I need the high-order bits in 32-bit R0 and the low-order bits in 32-bit R15. What's the simplest/fastest way to achieve this? I have no writable memory available. Thanks. .phsiii (getting frustrated trying to read PofOp, though it's not the book's fault!) ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN