I have enjoyed this thread and gotten a good chuckle from Dave Cole Steve
-----Original Message----- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf Of Charles Mills Sent: Friday, June 24, 2016 3:39 PM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: Simple assembler question Sure. We were referring to the rotate instructions, the new whiz-bang instructions like RISBLGZ. Charles -----Original Message----- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf Of Blaicher, Christopher Y. Sent: Friday, June 24, 2016 1:24 PM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: Simple assembler question For the SLLG, SRLG, SRAG and others, if you load the B register with the number of bits to shift and set the D value to zero, you can shift a variable number of bits without using an EXECUTE instruction. And there are SRL, SRDL, SRAG and SRLG that rotate right. Chris Blaicher Technical Architect Mainframe Development Syncsort Incorporated 50 Tice Boulevard, Woodcliff Lake, NJ 07677 P: 201-930-8234 | M: 512-627-3803 E: cblaic...@syncsort.com www.syncsort.com -----Original Message----- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf Of Charles Mills Sent: Friday, June 24, 2016 3:59 PM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: Simple assembler question > there are no versions of these instruction that rotate right... Blatant liberal* slant? Interesting. I was just looking at these instructions, which I have never used. The rotate count is an immediate operand, and not an immediate operand modifiable by Execute. Is there no way to rotate by an amount in a register, other than by modifying an instruction in storage, or with a loop? For those like me who have trouble remembering the mapping between facilities and models, the high word facility comes along with the z196. *Liberal in the American political sense, for our European and Asian members. Charles -----Original Message----- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf Of Tony Harminc Sent: Friday, June 24, 2016 12:15 PM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: Simple assembler question On 23 June 2016 at 17:51, Phil Smith III <li...@akphs.com> wrote: > > With all of the 273 new formats of LOAD, I assume this is hiding in there > somewhere: > I have a value in grande register 3. I need the high-order bits in > 32-bit R0 and the low-order bits in 32-bit R15. The RxSB... instructions are marvels in several ways, not least for having in some cases five operands, and in some cases 7-character names. And because there are some extended assembler mnemonics that bear no resemblance to the name or description of the base instruction. RISBLG[Z] is Rotate then Insert Selected Bits Low [and Zero remaining bits]. There is an extended mnemonic LLHFR (presumably Load Low from High Fullword Register) that generates RISBLGZ R1,R2,0,31,32 but even the RISBLGZ mnemonic is an extension of the base RISBLG that turns on the "Zero remaining bits" flag. These are actually great instructions for all sorts of things, and are recommended for performance reasons in Kevin Shum's IBM z Systems Processor Optimization Primer. If there's a catch, it's that they require the High Word Facility. I must admit I spent an embarassing number of minutes wondering why there are no versions of these instruction that rotate right... ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
