On 23 June 2016 at 17:51, Phil Smith III <li...@akphs.com> wrote: > > With all of the 273 new formats of LOAD, I assume this is hiding in there > somewhere:
> I have a value in grande register 3. I need the high-order bits in 32-bit R0 > and the low-order bits in 32-bit R15. The RxSB... instructions are marvels in several ways, not least for having in some cases five operands, and in some cases 7-character names. And because there are some extended assembler mnemonics that bear no resemblance to the name or description of the base instruction. RISBLG[Z] is Rotate then Insert Selected Bits Low [and Zero remaining bits]. There is an extended mnemonic LLHFR (presumably Load Low from High Fullword Register) that generates RISBLGZ R1,R2,0,31,32 but even the RISBLGZ mnemonic is an extension of the base RISBLG that turns on the "Zero remaining bits" flag. These are actually great instructions for all sorts of things, and are recommended for performance reasons in Kevin Shum's IBM z Systems Processor Optimization Primer. If there's a catch, it's that they require the High Word Facility. I must admit I spent an embarassing number of minutes wondering why there are no versions of these instruction that rotate right... Oh yes, so what I'm trying to say is that two variations on RISBxG[Z] would probably do just what you need. Tony H. ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
