> -----Original Message-----
> From: Deak, Imre <[email protected]>
> Sent: Thursday, January 8, 2026 8:06 PM
> To: Kandpal, Suraj <[email protected]>
> Cc: Kahola, Mika <[email protected]>; [email protected];
> [email protected]
> Subject: Re: [PATCH v2 12/15] drm/i915/lt_phy: Add verification for lt phy pll
> dividers
>
> On Tue, Jan 06, 2026 at 05:07:25AM +0000, Kandpal, Suraj wrote:
> > ...
> >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > index e33f6f48a6ce..13acfc7c0469 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > >
> > > ...
> > >
> > > +void intel_lt_phy_verify_plls(struct intel_display *display) {
> > > + intel_lt_phy_pll_verify_tables(display, xe3plpd_lt_dp_tables);
> > > + intel_lt_phy_pll_verify_tables(display, xe3plpd_lt_edp_tables);
> > > + intel_lt_phy_pll_verify_tables(display, xe3plpd_lt_hdmi_tables); }
> >
> > Same thing as the previous patch this is not needed. Moreover we do
> > not go through any algorithm for edp and dp tables for LT PHY hence
> > the Rate always matches. This patch should be dropped.
>
> Similarly to my comment on the previous patch, the tables entries should be
> kept correct even after they were initially added. So please don't drop this
> patch.
But testing DP eDP tables still does not make sense here since they don't go
through the traditional
HDMI algo that CX0 go through the clock rate in a way is signalled just by a
single entry of VDR0_CONFIG
So other than verifying table for HDMI the rest need not be done.
Regards,
Suraj Kandpal
>
> > Regards,
> > Suraj Kandpal
