Hi Vasili,
On 03/10/2021 10.32, vsurducan wrote:
Your program somehow works, however in my level of understanding it is not based on pure IOC. Once the IOCAF_IOCAF0 is set ( a IOC occured) you are testing again the level of RDY_IN which should not happen... IOC is the transition of IOCAF0 or INTCON_IOCIF to high (and I'm assuming only that should be testedsince the transition is defined by IOCAP/IOCAN).
In my provisional solution RDY_OUT is following RDY_IN. Therefore I enabled both rising and falling edge interrupts. Since there are no individual interrupt status bits for falling and rising edges the only way to determine which type of edge interrupt occured (which is needed to decide whether to set or reset RDY_OUT) I see no other way than looking at the current RDY_IN level.
Alternative: When you wish/need RDY_OUT be high during a specific time (20 ms) after each rising edge on RDY_IN then you might set a flag in the ISR, use a delay or timer and reset the flag in the forever loop.
According to the datasheet The "IOCIF Flag bit is read-only and cleared when all the Interrupt-On-Change flags in the IOCxF registers have been cleared by software", so that line can be commented, it will not be cleared. In fact this seems to be the real problem with the IOC module.
You are right, I overlooked that the IOCIF bit is read-only.
I can send you a scope image for positive edge detection to see the lost IOCs on positive edges if that helps.
Well, not necessary, I believe you! (I have a scope on my wish-list for a long time!). I'm just trying to help you with your problem. I'm not aware that I have a problem with IOC, and I'm using an 18F chip!
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