christophe leroy writes (edited):
> On a SA1100, the following prog last 13 seconds
> ldr r0,.L1
> eor r0,r0,r3
> ldr r1,.L2
> eor r1,r1,r3
> when I use
> ldr r0,.L1
> ldr r1,.L2
> eor r0,r0,r3
> eor r1,r1,r3
> instead, it last 10 seconds.
>
> Is that normal ? There should be no issue delay on ldr, shouldnt it ?
Interesting. Phil B. has sent me a patch which apparantly gives a
measurable speed improvement over by similar patches to the kernel.
According to both my SA-1100 and SA-110 documentation, there is no result
delay on either ldr nor the 'eor' instructions when the data resides in
the cache, which in your case it mostly always will be.
This means that the change you have made above should make not one ounce
of difference in the performance.
Issue Result
ldr r0,.L1 1 0
eor r0,r0,r3 1 0
ldr r1,.L2 1 0
eor r1,r1,r3 1 0
total: 4 0 = 4
ldr r0,.L1 1 0
ldr r1,.L2 1 0
eor r0,r0,r3 1 0
eor r1,r1,r3 1 0
total: 4 0 = 4
Therefore, the only explaination I can come up with is that there is an
error in the instruction timing documentation for all StrongARM parts,
or the documentation is lacking information on methods that can be used
to calculate the instruction timing.
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