Re: Instructions timing

[Philip Blundell]

>IIRC, when I was looking at the ARM gcc backend about a month ago I found no
>code to make this optimisation. I think I mentioned that here. Is it likely to
>produce > 1% speed increase?

In some cases, yes.  I got a speedup of a couple of percent on the lmbench 
`null syscall' test by taking account of load delay slots in the code in 
entry-*.S, but the execution path in question is only about 160 cycles anyway 
so. :-)

The ARM backend won't contain any code to explicitly make this optimisation - 
it's handled by sched.c based on information in arm.md.  See the (define_attr 
"ldsched") at about line 100 and the following stuff.

p.


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