Philip Blundell writes:
> The 0 result delay only applies to the updated base register. In other words,
> if you do `ldr r0, [r1], #4', the new r1 is available via a bypass for use by
> the following instruction.
>
> The destination register always has a result delay of either 1 or 2, depending
> on whether it's sign extended or zero extended. If no extension is needed I
> guess that counts as zero extension. I'm not sure why there is no bypass for
> this case, but I'm no semiconductor expert.
That also seems to be Deborah's understanding as well, and yes, it does appear
to fit all the facts... Shame the table's not clearer about it...
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