On Thu, May 06, 1999 at 09:08:41AM +0100, Nicholas Clark wrote:
> In the last mail Matthew Wilcox said:
>
> > Yes, this is normal; LDRs have a 1 cycle delay if the register is used
> > immediately. Last I heard; GCC did not reorder instructions to take
> > advantage of this.
>
> Q1: Where's the ARMLinux mailing list archive?
ftp.arm.linux.org.uk/pub/armlinux/m-list/
I'm going to subscribe my email address there to linux-arm and set up
a procmail filter this evening to have it auto-updated.
> IIRC, when I was looking at the ARM gcc backend about a month ago I found no
> code to make this optimisation. I think I mentioned that here. Is it likely to
> produce > 1% speed increase?
I think that's possible. Basically it means you can get an instruction
executed for free whenever you do a load instruction (if the instructions
can be scheduled right) and I think loads count for more than 10% of the
instructions executed (wild handwaving guess).
--
Matthew Wilcox <[EMAIL PROTECTED]>
"Windows and MacOS are products, contrived by engineers in the service of
specific companies. Unix, by contrast, is not so much a product as it is a
painstakingly compiled oral history of the hacker subculture." - N Stephenson
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