my 2 cents. On 06/06/2012 11:41 AM, Tony Lindgren wrote: > * CF Adad <cfa...@rocketmail.com> [120606 00:55]: >> >> Do you folks know of a good reference for properly calculating these GPMC >> settings? > > In theory you just need to know the timings of connected components, > then check which ones depend on cycles and which ones depend on time. > I afraid paper-and-pencil gpmc exercise is often required but after that it is more easy to see from charts if e.g. original settings were not optimal or too near to edge. Helps to understand and point possible problems on oscilloscope measurements too.
> Also take into account latencies added by level shifters if you have those. > Paul Walmsley noticed a few years ago that those affected the smsc911x > timings if not accounted for. > I've noticed the same. Even one-directional level shifters easily add a few ns and double amount in read operation since then there are two level shifters in a path: one in clk/cs/oe/etc cpu-to-chip signal and one on chip-to-cpu side. Pay also attention if there are extra latencies in chip. Chip memory reads/writes may be slower than chip register access (probably similar than smsc fifo issue what Tony mentioned earlier in this thread). -- Jarkko -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
