On Wed, Aug 22, 2018 at 09:28:01PM +0300, Sergei Shtylyov wrote: > The DM_CM_RST register actually has bits 0-31 defaulting to 1s and bits > 32-63 defaulting to 0s -- fix off-by-one in #define RST_RESERVED_BITS. > > Signed-off-by: Sergei Shtylyov <sergei.shtyl...@cogentembedded.com>
Reviewed-by: Wolfram Sang <wsa+rene...@sang-engineering.com> Suggesting stable.
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