On 08/22/2018 10:45 PM, Wolfram Sang wrote:
>>>> The DM_CM_RST register actually has bits 0-31 defaulting to 1s and bits
>>>> 32-63 defaulting to 0s -- fix off-by-one in #define RST_RESERVED_BITS.
>>>>
>>>> Signed-off-by: Sergei Shtylyov <sergei.shtyl...@cogentembedded.com>
>>>
>>> Reviewed-by: Wolfram Sang <wsa+rene...@sang-engineering.com>
>>>
>>> Suggesting stable.
>>
>> Stable looks at the Fixes: tags now. Should I add that?
>
> Yes, that would be great IMHO.
Fixes: 2a68ea7896e3 ("mmc: renesas-sdhi: add support for R-Car Gen3 SDHI DMAC")
Hopefully, Ulf uses patchwork. :-)
MBR, Sergei
