Re: how to enable cache for Pentium III (coppermine) chip

[tyson]

On 27 Feb, Terrell, Bill wrote:
> does anyone have any code which enables the L2 cache for the Pentium III
> (coppermine) chip?
>  
> Thanks,
> -bill

If you config the MTRRs and enable L1 cache you will be up and running.

All the code for this is in linuxbios now.

Ty

-- 
Tyson D Sawyer                             iRobot Corporation
Senior Systems Engineer                    Real World Interface Div.
[EMAIL PROTECTED]                         Robots for the Real World
603-532-6900 ext 206                       http://www.irobot.com