================
@@ -1878,20 +1878,31 @@ void
SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
Register DestReg, int FrameIndex,
const TargetRegisterClass *RC,
- Register VReg,
+ Register VReg, unsigned SubReg,
MachineInstr::MIFlag Flags) const {
MachineFunction *MF = MBB.getParent();
SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
MachineFrameInfo &FrameInfo = MF->getFrameInfo();
const DebugLoc &DL = MBB.findDebugLoc(MI);
unsigned SpillSize = RI.getSpillSize(*RC);
+ unsigned SubRegIdx = 0;
+ if (SubReg) {
+ uint64_t Mask = RI.getSubRegIndexLaneMask(SubReg).getAsInteger();
+ assert(llvm::popcount(Mask) % 2 == 0 &&
+ "expected only 32-bit subreg access");
+
+ // For subreg reload, identify the start offset. Each 32-bit register
+ // consists of two regunits and eventually two bits in the Lanemask.
+ SubRegIdx = llvm::countr_zero(Mask) / 2;
----------------
arsenm wrote:
Don't rely on the bit layout of the mask
https://github.com/llvm/llvm-project/pull/175002
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