================
@@ -727,6 +763,9 @@ static constexpr DecoderListEntry DecoderList32[]{
{DecoderTableXSMT32, XSMTGroup, "SpacemiT extensions"},
{DecoderTableXAIF32, XAIFGroup, "AI Foundry extensions"},
// Standard Extensions
+ {DecoderTableRVYOnly32,
+ {RISCV::FeatureStdExtY},
+ "RVY-only standard 32-bit instructions"},
----------------
arichardson wrote:
New workaround: split it into SRLIY64 and SRLIY32 which now has fixed bits in
these positions so the decoder checks them before checking SRLI:
```
5, 132, 1, // 2089: case 0x5: {
OPC_SwitchField, 26, 6, // 2092: switch Inst[31:26] {
0, 16, // 2095: case 0x0: {
OPC_Scope, 10, // 2097: try {
OPC_CheckField, 20, 6, 32, // 2099: check Inst[25:20] ==
0x20
OPC_CheckPredicate, 41, // 2103: check predicate 41
OPC_Decode, 244, 123, 18, // 2105: decode to SRLIY32
using decoder 18
// 2105: } else try {
OPC_Decode, 242, 123, 15, // 2109: decode to SRLI using
decoder 15
// 2109: }
// 2109: }
1, 10, // 2113: case 0x1: {
OPC_CheckPredicate, 42, // 2115: check predicate 42
OPC_CheckField, 20, 6, 0, // 2117: check Inst[25:20] ==
0x0
OPC_Decode, 245, 123, 19, // 2121: decode to SRLIY64
using decoder 19
// 2121: }
```
https://github.com/llvm/llvm-project/pull/176871
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