https://github.com/arichardson updated https://github.com/llvm/llvm-project/pull/176871
>From 769703cabca94a8eab5c8c783fc31d5d60d93bae Mon Sep 17 00:00:00 2001 From: Alex Richardson <[email protected]> Date: Wed, 21 Jan 2026 11:02:23 -0800 Subject: [PATCH] clang-format Created using spr 1.3.8-beta.1 --- llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 57e6350b99b8f..cbb9796f4c089 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -80,8 +80,8 @@ LLVMInitializeRISCVDisassembler() { template <unsigned BaseReg> static DecodeStatus decodeGPRLikeRC(MCInst &Inst, uint32_t RegNo, - uint64_t Address, - const MCDisassembler *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { bool IsRVE = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureStdExtE); if (RegNo >= 32 || (IsRVE && RegNo >= 16)) _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
