================ @@ -0,0 +1,108 @@ +//===-- RISCVInstrInfoY.td - RISCV instructions -------------*- tblgen-*---===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Instruction Formats +//===----------------------------------------------------------------------===// + +include "RISCVInstrFormatsY.td" + +//===----------------------------------------------------------------------===// +// Instruction Class Templates +//===----------------------------------------------------------------------===// + +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { + class RVY_r<bits<5> funct5, string opcodestr, DAGOperand rdOp = GPR, + DAGOperand rs1Op = YGPR> + : RVYInstSrcDst<0x8, funct5, 0x0, OPC_OP, (outs rdOp:$rd), + (ins rs1Op:$rs1), opcodestr, "$rd, $rs1">; + class RVY_rr<bits<7> funct7, bits<3> funct3, string opcodestr, + DAGOperand rdOp = YGPR, DAGOperand rs1Op = YGPR, + DAGOperand rs2Op = GPR> + : RVInstR<funct7, funct3, OPC_OP, (outs rdOp:$rd), + (ins rs1Op:$rs1, rs2Op:$rs2), opcodestr, "$rd, $rs1, $rs2">; + class RVY_ri<bits<3> funct3, RISCVOpcode opcode, string opcodestr, + DAGOperand rdOp = YGPR, DAGOperand rs1Op = YGPR> + : RVInstI<funct3, opcode, (outs rdOp:$rd), + (ins rs1Op:$rs1, simm12_lo:$imm12), opcodestr, + "$rd, $rs1, $imm12">; + class RVY_setboundsimm<string opcodestr> + : RVYInstSetBoundsImmFmt<(outs YGPR:$rd), + (ins YGPR:$rs1, ybndsw_imm:$imm), opcodestr, + "$rd, $rs1, $imm">; +} // hasSideEffects = 0, mayLoad = 0, mayStore = 0 + +let Predicates = [HasStdExtY] in { + // + // Instructions to Update The Capability Pointer + // + let isReMaterializable = true, isAsCheapAsAMove = true in { + def ADDY : RVY_rr<0x6, 0x0, "addy", YGPR, YGPR, GPRNoX0>; + def ADDIY : RVY_ri<0x2, OPC_OP_IMM_32, "addiy">; ---------------- lenary wrote:
I think conflicts are only detected when two instructions have a wildcard bit at the same position, not when one has a fixed bit and the other has a wildcard bit (it's assumed the one with the fixed bit is the more specific decode and used). We rely on this behaviour in a bunch of places, where we have `GPRNoX0` fields (5 bits, all wildcard), and reuse the `0b00000` encoding for another instruction. In these cases, we are getting the correct behaviour. For more complex cases, we should be setting `hasCompleteDecoder = false`, so that the decoder can try several operand/instruction decoders and the failure of the first decoder is not treated as a failure of decoding, it will continue trying the rest. https://github.com/llvm/llvm-project/pull/176871 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
