https://github.com/arichardson updated https://github.com/llvm/llvm-project/pull/176871
>From 769703cabca94a8eab5c8c783fc31d5d60d93bae Mon Sep 17 00:00:00 2001 From: Alex Richardson <[email protected]> Date: Wed, 21 Jan 2026 11:02:23 -0800 Subject: [PATCH 1/2] clang-format Created using spr 1.3.8-beta.1 --- llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 57e6350b99b8f..cbb9796f4c089 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -80,8 +80,8 @@ LLVMInitializeRISCVDisassembler() { template <unsigned BaseReg> static DecodeStatus decodeGPRLikeRC(MCInst &Inst, uint32_t RegNo, - uint64_t Address, - const MCDisassembler *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { bool IsRVE = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureStdExtE); if (RegNo >= 32 || (IsRVE && RegNo >= 16)) >From 0aa408299b9ef5dec49426a41ab0929a4cf193cb Mon Sep 17 00:00:00 2001 From: Alex Richardson <[email protected]> Date: Thu, 22 Jan 2026 12:30:18 -0800 Subject: [PATCH 2/2] inline format templates that are used only once and fix packy test Created using spr 1.3.8-beta.1 --- llvm/lib/Target/RISCV/RISCVInstrInfoY.td | 46 ++++++++----------- .../MC/RISCV/rvy/rvy-valid-mode-independent.s | 4 +- 2 files changed, 21 insertions(+), 29 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoY.td b/llvm/lib/Target/RISCV/RISCVInstrInfoY.td index e6f73d645cc9b..f092df82bd9c3 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoY.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoY.td @@ -51,7 +51,7 @@ def uimm7_srliy : RISCVUImmOp<7>, ImmLeaf<XLenVT, [{ } //===----------------------------------------------------------------------===// -// Instruction Formats +// Instruction Formats and class templates //===----------------------------------------------------------------------===// // Like an RVInstR, except rs2 is now an additional function code. @@ -70,28 +70,6 @@ class RVYInstSrcDst<bits<7> funct7, bits<5> funct5, bits<3> funct3, let Inst{6-0} = opcode.Value; } -class RVYInstBNDSWIFmt<dag outs, dag ins, string opcodestr, string argstr> - : RVInstIBase<0b011, OPC_OP_IMM_32, outs, ins, opcodestr, argstr> { - bits<5> rd; - bits<5> rs1; - bits<10> imm; - - let Inst{31-30} = 0b00; - let Inst{29-20} = imm; -} - -class RVYInstSRLIYFmt<bits<7> imm, dag outs, dag ins, string opcodestr, - string argstr> - : RVInstIBase<0b101, OPC_OP_IMM, outs, ins, opcodestr, argstr> { - bits<7> shamt = imm; - let Inst{31-27} = 0b00000; - let Inst{26-20} = shamt; -} - -//===----------------------------------------------------------------------===// -// Instruction Class Templates -//===----------------------------------------------------------------------===// - let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { class RVY_r<bits<5> funct5, string opcodestr, DAGOperand rdOp = GPR, DAGOperand rs1Op = YGPR> @@ -108,11 +86,25 @@ class RVY_ri<bits<3> funct3, RISCVOpcode opcode, string opcodestr, (ins rs1Op:$rs1, simm12_lo:$imm12), opcodestr, "$rd, $rs1, $imm12">; class RVY_bndswi<string opcodestr> - : RVYInstBNDSWIFmt<(outs YGPR:$rd), (ins YGPR:$rs1, ybndsw_imm:$imm), - opcodestr, "$rd, $rs1, $imm">; + : RVInstIBase<0b011, OPC_OP_IMM_32, (outs YGPR:$rd), + (ins YGPR:$rs1, ybndsw_imm:$imm), opcodestr, + "$rd, $rs1, $imm"> { + bits<5> rd; + bits<5> rs1; + bits<10> imm; + + let Inst{31-30} = 0b00; + let Inst{29-20} = imm; +} class RVY_srli<string opcodestr, bits<7> imm> - : RVYInstSRLIYFmt<imm, (outs GPR:$rd), (ins YGPR:$rs1, uimm7_srliy:$shamt), - opcodestr, "$rd, $rs1, $shamt">; + : RVInstIBase<0b101, OPC_OP_IMM, (outs GPR:$rd), + (ins YGPR:$rs1, uimm7_srliy:$shamt), opcodestr, + "$rd, $rs1, $shamt"> { + bits<7> shamt = imm; + + let Inst{31-27} = 0b00000; + let Inst{26-20} = shamt; +} } // hasSideEffects = 0, mayLoad = 0, mayStore = 0 let Predicates = [HasStdExtY] in { diff --git a/llvm/test/MC/RISCV/rvy/rvy-valid-mode-independent.s b/llvm/test/MC/RISCV/rvy/rvy-valid-mode-independent.s index 1023d6e6a06df..95d20f454fcee 100644 --- a/llvm/test/MC/RISCV/rvy/rvy-valid-mode-independent.s +++ b/llvm/test/MC/RISCV/rvy/rvy-valid-mode-independent.s @@ -66,14 +66,14 @@ ymv a0, a0 # CHECK-ASM-NEXT: # <MCOperand Imm:0>> mv a0, a0 # CHECK-NEXT: packy a0, a0, a0 -# CHECK-ASM-SAME: # encoding: [0x33,0x35,0xa5,0x0c] +# CHECK-ASM-SAME: # encoding: [0x33,0x35,0xa5,0x08] # CHECK-ASM-NEXT: # <MCInst #[[#]] PACKY{{$}} # CHECK-ASM-NEXT: # <MCOperand Reg:X10_Y> # CHECK-ASM-NEXT: # <MCOperand Reg:X10_Y> # CHECK-ASM-NEXT: # <MCOperand Reg:X10>> packy a0, a0, a0 # CHECK-NEXT: packy a0, a0, a0 -# CHECK-ASM-SAME: # encoding: [0x33,0x35,0xa5,0x0c] +# CHECK-ASM-SAME: # encoding: [0x33,0x35,0xa5,0x08] # CHECK-ASM-NEXT: # <MCInst #[[#]] PACKY{{$}} # CHECK-ASM-NEXT: # <MCOperand Reg:X10_Y> # CHECK-ASM-NEXT: # <MCOperand Reg:X10_Y> _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
