> -----Original Message----- > From: Brian Brooks [mailto:brian.bro...@linaro.org] > Sent: Friday, January 20, 2017 7:47 PM > To: Francois Ozog <francois.o...@linaro.org> > Cc: Bill Fischofer <bill.fischo...@linaro.org>; Joe Savage > <joe.sav...@arm.com>; Maxim Uvarov <maxim.uva...@linaro.org>; Savolainen, > Petri (Nokia - FI/Espoo) <petri.savolai...@nokia-bell-labs.com>; lng- > o...@lists.linaro.org; nd <n...@arm.com> > Subject: Re: [lng-odp] 32-bit support in examples > > CAS is a universal primitive in the sense that you can construct those > RMW ops by speculatively computing the updated value and the CAS to > atomically update the value (in a retry loop). LL/SC also universal, > but different behavior. Both are not the same as an atomic op > performed deeper in the memory system. > > To Petri's point about ODP not supporting 128b atomics, which compiler > does not support the __atomic_xxx built-ins or the __int128 128b > variable? This has impact on portability and should be explicitly > known; is it the microblaze compiler?
Any atomics can be emulated in SW (using compiler built-ins or locks directly). The point here is the missing HW support: * E.g. MIPS, Power, ARMv7 do not have 128 bit CAS * 128 bit fetch-and-add is not supported in any of the architectures We need to ensure on any operations added that those can be implemented efficiently on most of the targets. -Petri > > On Fri, Jan 20, 2017 at 7:36 AM, Francois Ozog <francois.o...@linaro.org> > wrote: > > well, yes. But that is the only atomic operation supported. No add, sub, > > inc, xadd, bit operations.... > > > > Le ven. 20 janv. 2017 à 14:31, Joe Savage <joe.sav...@arm.com> a écrit : > > > >> > I wonder what processor supports 128 bits atomics. As far as I know > Intel > >> > >> > does not support it. Lock prefix is not allowed on SSE instructions. > >> > >> > >> > >> Actually, Intel does support them through a locked cmpxchg16b. And > ARMv8 > >> > >> through load exclusive pair and store exclusive pair. > >> > >>
