Although not mentioned (neither on Doug's cookbook) I have always supposed was more likely the c++ default for both weak/strong CAS ie seq_cst memory ordering. To make this question more mechanical sympathy focused: on hardware level what happen? I would be curious to know both x86/arm versions for this, what kind of memory reordering are guaranteed...
Most people says that a failed CAS cost much less then one that succeed, but just like a load or more? Probably the success will cause invalidation of all the caches that reference the cache line changed, but the failed case should lock (on x86) it and AFAIK locks (hw or SW) are not well known to be scalable and performant :) -- You received this message because you are subscribed to the Google Groups "mechanical-sympathy" group. To unsubscribe from this group and stop receiving emails from it, send an email to mechanical-sympathy+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/mechanical-sympathy/caebab48-f88f-477d-bc8e-95702e45bc76%40googlegroups.com.
