On Sun, Feb 28, 1999 at 07:21:51PM -0700, Aaron Blosser <[EMAIL PROTECTED]> wrote:
>
> Also FWIW, the package of a PII is nothing more than the CPU and a couple of
> chips for the L2 cache. It's *possible* that the first Celerons were PII's
> with failed L2 cache chips that were then disabled, but not likely. Since
> they are seperate chips and are assembled in the package, each chip is
> tested prior to packaging and there wouldn't really be any PII's with bad
> cache.
I suspect the problem was with the cache controller on the CPU, much like...
> the 486sx which were 486DX chips with the FPU purposely disabled.
... which were disabled because they failed QA testing.
Bryan
--
Bryan Fullerton http://www.samurai.com/
Owner, Lead Consultant http://www.feh.net/
Samurai Consulting http://www.icomm.ca/
"No, we don't do seppuku." Can you feel the Ohmu call?
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